Powerlogic circuit monitor series 2000 reference manual

At step 10 the power of the three-phase circuit is calculated using the computed power factors for phases A, B, and C. In an embodiment, the routine is idled at step until a timer restarts the cycle at step In an alternate embodiment, the routine continually cycles, passing control from step to step In one embodiment, the system 8 has already determined that one or more wiring errors has occurred, and instructs the multiplexer 22 to adjust the addresses so that the readings are made in the proper order.

In yet another embodiment, the system 8 periodically or at predetermined intervals checks the phase relationships to verify they are not outside of expected ranges. At step , the analog multiplexer 22 selects the address of the voltage line V 1 -VN corresponding to the phase parameter to be analyzed.

For example, to analyze phase B, the address corresponding to voltage line V 2 is selected by the multiplexer 22 under command of the processor If a wiring error has been previously detected, a different address may be selected. For example, if V 1 and V 2 were reversed, the address of V 2 actually corresponds to the voltage line V 1.

In such a case, the processor 30 would instruct the multiplexer 22 to select the address corresponding to voltage line V 1 in order to compute the power factor for phase B. As described in connection with FIG. The amplified signal is sampled by the sample and hold circuit 26 and digitized by the ADC The digital signal is provided to the processor 30 in step The resulting voltage sample may be stored in a memory location.

Similarly, at step the processor 30 instructs the analog multiplexer 22 to select the address of the current line I 1 -IN corresponding to the phase parameter to be analyzed. The resulting signal is amplified and digitized by the ADC 28 and provided to the processor 30 in step The resulting current sample may be stored in a memory location.

The processor 30 applies a Fast Fourier Transform algorithm on the voltage and current samples to obtain their phase angles. At step , the processor optionally checks the relationship of the phase angles. As noted above, the expected power factor on each phase is assumed to be within certain bounds, normally about 0. If the relationship is outside of an expected range, then a wiring error or other circuit failure may be indicated. In the case of a wiring error, the error can be detected at optional step and a new current line address I 1 -IN can be tried until a reading is obtained indicating a proper phase relationship.

For example, in the wiring, error described in connection with FIG. In this manner, although the I 2 and I 3 lines are swapped, the data nonetheless arrives in the memory map in the expected sequence. The power factor subroutine is exited at step The invention generally may be used in meters or other devices which monitor electricity or quantities with known phase relationships such as power systems.

The invention offers greater flexibility in auto configuration or self correction for wiring errors without causing downtime to the end user. While a 3-phase power system has been described herein, it is understood that the system 8 can be extended to any number of inputs which have fixed phase relationships.

As indicated above, the invention may have other uses or advantages as well. For example, rather than correcting for incorrect wiring sequences, the invention may be used to automatically configure any given wire sequence to a desired input sequence and any type of metering or monitoring situation where the quantities to be monitored have known phase or relationships which can be detected by the monitoring process.

In addition, the invention advantageously can solve for problems of coupling between channels. While particular embodiments and applications of the present invention have been illustrated and described, it is to be understood that the invention is not limited to the precise construction and compositions disclosed herein and that various modifications, changes, and variations may be apparent from the foregoing descriptions without departing from the spirit and scope of the invention as defined in the appended claims.

All rights reserved. Login Sign up. Search Expert Search Quick Search. Method for detecting and correcting wiring errors in power monitoring applications.

United States Patent A three-phase monitoring system for detecting and dynamically correcting wiring errors in an electrical circuit. The system includes a voltage divider circuit and a current transformer circuit connected to three voltage channels and three current channels, respectively.

Samples of the voltages and currents are held in respective sample and hold circuits, which are provided to an analog multiplexer. The analog multiplexer is controlled by a processor, and is coupled to gain and filter circuitry, sample and hold circuitry, and to an analog-to-digital converter ADC. If the power factor is outside of an expected range, the processor dynamically changes the addresses assigned to the channels such that the data arrives in the processor in an expected sequence.

Click for automatic bibliography generation. Download PDF Andover, MA, US. What is claimed is: 1. A method for detecting a wiring error in an electrical circuit monitored by a power-monitoring system, comprising: addressing an analog multiplexer under control of a processor according to a first address to select a first input carrying an analog voltage signal from said electrical circuit monitored by said power-monitoring system; addressing said analog multiplexer according to said first address to select a second input carrying an analog current signal corresponding to said analog voltage signal; calculating the power factor corresponding to said analog voltage signal and said analog current signal; comparing said power factor with an expected power factor range; and changing said first address associated with said first input or said second input to a second address in response to said comparing when said power factor exceeds said expected power factor range such that said second address differs from said first address.

The method of claim 1, wherein said calculating is carried out using a Fast Fourier Transform algorithm. The method of claim 1, wherein said expected power factor range is substantially 0. The method of claim 1, further comprising storing a value indicative of one of said analog voltage signal and said analog current signal in a memory. The method of claim 1, further comprising: calculating the displacement angles of the respective phases corresponding to said analog voltage signal and said analog current signal; determining whether the displacement angle corresponding to said analog voltage signal is within a first expected range; and determining whether the displacement angle corresponding to said analog current signal is within a second expected range.

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